1. Field of Invention
The present invention relates to an Electronic Design Automation (EDA) method. More particularly, the present invention relates to an automatic power grid synthesis method and a computer readable recording medium for storing a program thereof.
2. Description of Related Art
The electronic industry develops rapidly with the assistance of computer science. For example, Electronic Design Automation (EDA) makes use of the operation ability to aid the design and simulate the electronic circuit for research engineers. Especially, the integrated circuit research needs various automatic tools to aid such work as function tests, synthesis, line layout, electronic analysis and simulation. Additionally, as the trend of the circuit densification and the timing requirement of product launches in the market, it is an important subject for how to research & develop the most economically beneficial chip products within a shortest period of time.
In circuit designing process, the specification of the power line (power grid) and the disposed position must be laid out in order to supply enough power for all the power consumption modules & devices. For a long time, all the power grid forming tools apply design-independent rule-based design method (whatever for power ring/line or power net). The method includes the following steps: (1) form the power grid in accordance with some internal rules; (2) then, verify the quality of the formed power grid or net by rail analysis tool. If the testing result can not meet the required specification, then (3) find out the hot spot (namely, the weakness point) and strengthen it.
However, power grid will occupy the line layout resource, so that, in some circuits, the chip area must be enlarged to meet the voltage drop specification between the power pin and the internal circuit without affecting the common signal circuit line layout, which increases the manufacturing cost. Therefore, in the precondition of meeting the voltage drop specification between the power pin and the internal circuit, the smaller the area of the power grid, the better. The disadvantages of the current known method for forming the power grid include: (1) the methods can only find out the weakness point(s) of the formed power grid, but can not simplify the power grid area of the small power consumption area; (2) the method first forms the power grid or net in accordance with manually decided specification; then finds out the weakness point(s) by verification and manually enlarges the power grid dimension of the power grid; such repeating operation prolongs the circuit design processing cycle; (3) the known method of forming power grid is design-independent, which applies the common power grid architecture on all the circuit design configurations, that it can not suit the design requirement.